Two-transistor memory cells relate to non-volatile memory cells which comprise at least one access transistor and at least one memory transistor. Non-volatile memory cells are used in a wide variety of commercial and military electronic devices and equipment, such as RFID/NFC, smart cards, automotive applications, mobile phones, radios or digital cameras. The market for these electronic devices continually demands devices with a lower voltage, lower power consumption and decreased chip size.
The access transistor typically comprises diffusion implants, which can act as source or drain, an access channel region and an access gate. The access channel region is often arranged intermediate the diffusion regions of the access transistor. The memory transistor typically comprises diffusion implants, which can act as a source or a drain, a memory channel region, a memory gate stack and a memory gate. The memory channel region is often arranged intermediate the diffusion implants. The memory gate stack is typically located above the memory channel region and is arranged for storing electronic charge. Typically, the memory gate stack comprises a stack of layers comprising a first insulating layer, a charge storage layer and a second insulating layer, wherein the first insulating layer is arranged intermediate the memory channel region and the charge storage layer, and the second insulating layer is arranged intermediate the charge storage layer and the memory gate. Under control of a gate voltage of the memory transistor, i.e. the memory gate voltage, the memory gate stack can be programmed and erased.
In SONOS (Semiconductor Oxide-Nitride-Oxide Semiconductor) memory cell devices, the memory gate stack comprises at least a stack of a bottom silicon dioxide layer, a charge trapping silicon nitride layer and a top silicon dioxide layer, also known as an ONO stack. SONOS memory cell devices are used in view of scaling, as reduced program and erase voltages can be obtained. However, as such low power SONOS memory cells, operated by direct tunnelling, suffer from retention problems, high-K dielectrics in combination with metal gates are used to replace the silicon oxide layers. Such non-volatile memory cells, wherein the silicon oxide layers are replaced by HfSiOx are usually referred to as SHINOS memory transistors. However, while such SHINOS memory transistors have the desired properties in terms of program and erase characteristics, endurance and retention, such memory transistors with a high-K gate dielectric provided as HfSiOx suffer from inherent reliability problems.
Accordingly, it is the object of the invention to provide a multi-transistor, e.g. two-transistor memory cell and a method for manufacturing a multi-transistor, e.g. two-transistor memory cell that provides a good reliability as well as to arrays of such cells in memory devices.
An advantage of the present invention can be the provision of reduced program and erase voltages for a multi-transistor, e.g. two-transistor memory cell.